1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, a high-speed micro field effect transistor which retains mechanical stress in semiconductor regions constituting a channel and which comprises silicided source/drain electrodes, and also relates to a manufacturing method thereof.
2. Description of the Related Art
As evident in the prevalence of high-speed mobile communications, we are experiencing a remarkable transition towards an information-intensive society owing to the realization of sophisticated ultra-high-speed semiconductor devices. Naturally, demands for a higher speed operation, miniaturization of the physical dimensions, and large-scale as well as single-chip integration of the semiconductor devices are ever increasing. In order to meet these demands, however, realization of the higher speed operation and the miniaturization of MOS-type field effect transistors (hereinafter referred to as MOSFET's), which are the main components of these semiconductor devices, need to overcome various difficulties.
In order to achieve a higher speed operation of the MOSFET, one can take advantage of mobility enhancement by mechanical stress, a phenomenon in which electronic states in a conduction band and a valence band of a semiconductor are modulated and mobility of carriers (electrons and holes) is increased when mechanical stress is applied to a channel semiconductor portion (e.g., refer to H. Irie et al., IEDM Tech. Dig. pp. 225 to 228, 2004).
One may attempt to generate such mechanical stress in the channel portion after the completion of the MOSFET structure by depositing an additional insulating film having high internal stress over the entire MOSFET structure. Nonetheless, with this method, most of the stress of the film is to be applied to a gate electrode. Thus, it is not possible to effectively generate the required stress in the channel portion. Furthermore, eventually, electrical contacts to the source and drain regions must be established by forming contact holes through this stress-yielding insulating film over the source and drain regions.
If the sizes of the contact holes are comparable to the sizes of the source and drain regions (which is the very case of the small miniaturized MOSFET's), most of the deposited film containing the stress is to be removed from the MOSFET. Hence, practically, stress is not generated in the channel portion.
As shown in FIG. 28, such dissipation of the stress can be avoided by replacing the source/drain regions with a semiconductor material 1 (e.g., a eutectic of Si and Ge, hereinafter abbreviated as SiGe) which is different from the channel semiconductor (Si) and having a high internal stress (e.g., refer to T. Ghani et al., IEDM Tech. Dig. pp. 978 to 980, 2003). Because the stress-yielding semiconductor material replacing the source/drain regions comes to directly compress or expand the channel portion, stress is effectively generated in the channel portion.
In order to replace the source/drain regions with a stress-exerting semiconductor, first, the source/drain regions in the substrate semiconductor (Si) surface must be etched away to form recesses in the corresponding surface regions. Subsequently, a crystalline semiconductor material having a lattice constant different from that of the substrate semiconductor may be epitaxially grown to selectively fill up the aforementioned recesses. Naturally, since the source/drain electrodes are formed of a semiconductor of a kind different from the substrate semiconductor, junctions between the substrate semiconductor and the source/drain electrode semiconductor become so-called hetero-junctions 2 (i.e., junctions formed between different materials).
However, a hetero-junction between crystals having different lattice constants is prone to a generation of a great number of crystal defects 3 along the junction. Thus, a large junction leakage current comes to flow from the source/drain electrode to the substrate semiconductor through these defects. In order to suppress the junction leakage current associated with the hetero-junctions, it is necessary to entirely enclose these hetero-junctions by p-n junctions 4 by introducing a different type of conductive impurities from that in the substrate semiconductor. The dopants must be incorporated in wider and deeper regions, enveloping the heterogeneous source/drain semiconductor and extending into the substrate semiconductor, so that the hetero-junctions are completely contained within the doped regions and, therefore, electrically isolated from the substrate semiconductor by these p-n junctions formed between the doped regions and the substrate.
However, conductive impurities introduced in the vicinity of the hetero-junction full of crystal defects, are known to diffuse very rapidly due to the crystal defects (this is called transient enhanced diffusion). It entails that the depth of the p-n junction to envelope the hetero-junction becomes deeper than the intended depth. In addition, it is known that a conductive impurity such as As diffuses in SiGe at a high speed, and the depth of the p-n junction will become even deeper.
Once the p-n junctions of the source/drain regions deepen, the electric field at the source and drain electrodes starts to influence the electric potential around the center of the channel portion and, thus, comes to reduce the threshold voltage of the MOSFET (i.e., short channel effect). If the threshold voltage comes to differ from the intended value, the resulting unexpected device operation impairs the designed function of the entire circuit. Moreover, with the short channel effect, the threshold voltage comes to depend on the physical length of the gate electrode very sharply. Therefore, even a slight deviation in the gate length due to practically inevitable processing variation during the gate formation cannot be tolerated to achieve the intended characteristics of the device, which significantly compromises the manufacturability of the circuit.
The only way to avoid this devastating short channel effect is shallowing the pn-junction depth. Concordantly, the hetero-junctions and the stress-yielding semiconductor material, which must be entirely enveloped by the pn-junctions to suppress the leakage current, have to be also kept shallow and thin. Nonetheless, thinning of the stress-yielding semiconductor material constituting the hetero-junctions may invalidate the very purpose for the introduction of the material, because the thin “stressor” (i.e., stress-yielding semiconductor material) cannot simply generate sufficient stress in the channel portion to increase the carrier mobility, dashing the initial intention for obtaining high-speed operation of the devices.
In addition, the conductivity of the source/drain electrodes causes yet another intractable problem when the heterogeneous stressor is employed as a source/drain electrode material. First, in order to ensure high-speed operation of the device, the electrical resistance of the source/drain electrode must be kept low so that high-speed transmission of an electrical signal along the channel is not retarded in the source/drain electrodes. The reduction of the electrical resistance of the source/drain becomes especially critical when the source/drain electrodes are force to be thin to avoid the short channel effect as explained above. Conventionally, the reduction of the electrical resistance of the source/drain is achieved by forming a compound between a metallic material and the source/drain-constituting semiconductor by selectively reacting the upper surfaces of the source/drain region with a metal.
One of the metal suitable for this purpose is Ni, which does not show an increase in electrical resistance when it is formed in a thin-line shape (thin-line effects) and, thus, is applicable to a miniaturized LSI. However, when Ni reacts with a semiconductor material other than Si, for example, SiGe, the reaction is unstable and does not proceed uniformly. The resultant interface between the source/drain-constituting semiconductor material and the metallic compound 5 thereon becomes very rough. The high asperity of the interface leads to a stochastic formation of spike-shaped deep protrusions of the metallic compound 6, penetrating through the “stressor” (i.e., stress-yielding and source/drain-constituting semiconductor material) and even reaching the underlying semiconductor beyond the deeper p-n junction. Needless to say, such protrusions generate significant junction leakage. Moreover, the non-uniformly-formed metallic compound may well agglomerate into island shapes or break off into disconnected patches so that the electrical resistance increases precipitously.
In addition, it is known that a compound of Ni and SiGe reduces the internal stress possessed by SiGe. Therefore, even if the stress-yielding semiconductor is employed as a source/drain material to generate stress, sufficient stress cannot be generated in the channel portion, and the mobility is not increased.
Now it becomes clear that, when a stress-yielding semiconductor with high internal stress is employed as a source/drain material to generate stress in the channel portion and, thus, enhance the mobility of a MOSFET, generation of sufficient stress, avoidance of the short channel effect, and suppression of the junction leakage cannot be realized simultaneously. In addition, it becomes difficult to simultaneously achieve reduction of the electrical resistance of the source/drain electrodes, suppression of the junction leakage and retention of stress.
Therefore, an ultra-high-speed micro MOSFET in which both the short channel effect and the junction leakage are suppressed, resistance is reduced in the source/drain electrode, and the mobility is increased by the stress imposed on the channel portion, is much desired and there has been a need to establish a practical manufacturing method thereof.